one. The basic concept of vias
Vias are one of the most important components of multi-layer PCBs. The cost of drilling usually accounts for 30% to 40% of PCB manufacturing cost. In simple terms, every hole in the PCB can be called a via. From a functional point of view, vias can be divided into two categories: one is used as the electrical connection between layers, and the other is used as a device for fixing or positioning. From the process point of view, these vias are generally divided into three categories, namely, blind vias, buried vias, and through vias. The blind holes are located on the top and bottom surface of the printed circuit board and have a certain depth, which is used for the connection of the surface lines and the underlying inner layer lines. The depth of the holes does not usually exceed a certain ratio (aperture). The buried hole refers to the connection hole located in the inner layer of the printed circuit board, and it does not extend to the surface of the circuit board. The above two kinds of holes are all located in the inner layer of the circuit board. Before the lamination, the through-hole forming process is used to complete, and several inner layers may be overlapped during the formation of the via hole. The third type is called vias, which pass through the entire circuit board and can be used to implement internal interconnects or as mounting holes for components. Since vias are easier to implement and lower in cost, most printed circuit boards use it instead of the other two vias. The following vias, unless otherwise specified, are considered as vias.
From the design point of view, a via is mainly composed of two parts, one is the drill hole in the middle and the other is the pad area around the drill hole. The size of these two parts determines the size of the via hole. . Obviously, in high-speed, high-density PCB designs, designers always hope that the smaller the via, the better, so that the board can leave more wiring space. In addition, the smaller the via hole, its own parasitic capacitance. The smaller, more suitable for high-speed circuits. However, the reduction of the hole size brings about an increase in cost, and the size of the via hole cannot be reduced indefinitely. It is limited by the drilling and plating techniques: the smaller the hole, the smaller the hole is. The harder the hole processing process, the longer it takes and the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drill hole, there is no guarantee that the hole wall can be evenly plated with copper. For example, the normal thickness of a 6-layer PCB (via hole depth) is about 50 Mil, so the minimum hole diameter that a typical PCB manufacturer can provide is only 8 Mil.
two. Through-hole parasitic capacitance
The via hole itself has parasitic capacitance to ground. If the diameter of the via hole on the grounding layer is known as D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the substrate is ε, then the parasitic capacitance of the via is similar to:
C=1.41εTD1/(D2-D1)
The main effect of the via's parasitic capacitance on the circuit is to extend the signal's rise time and reduce the circuit's speed. For example, for a PCB board with a thickness of 50 Mil, if you use a via with an inner diameter of 10 Mil and a pad diameter of 20 Mil, and the distance between the pad and the copper area of ​​the ground is 32 Mil, we can use the above formula to approximate the via The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF. The amount of rise time variation caused by this capacitance is: T10-90=2.2C(Z0/2)=2.2 X0.517x(55/2)=31.28ps. From these values, it can be seen that although the effect of the slowing of the rise delay caused by the parasitic capacitance of a single via is not obvious, if the vias are used multiple times in the trace to switch between layers, the designer should carefully consider.
three. Through-hole parasitic inductance
Similarly, there are parasitic inductances in the vias as well as parasitic inductances. In the design of high-speed digital circuits, the parasitic inductance of the vias is often greater than the parasitic capacitance. Its parasitic series inductance weakens the contribution of the bypass capacitor and attenuates the filtering effect of the entire power system. We can use the following formula to simply calculate the parasitic inductance of a via:
L=5.08h[ln(4h/d)+1]
Where L is the inductance of the via, h is the length of the via, and d is the diameter of the center hole. It can be seen from the equation that the diameter of the via has little effect on the inductance, and the effect on the inductance is the length of the via. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050 [ln(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1 ns, then its equivalent impedance is: XL = πL/T10-90 = 3.19 Ω. This kind of impedance can't be neglected when there is high-frequency electric current passing through, especially should pay attention to, when the bypass electric capacity needs to pass through two through holes while connecting the power layer and stratum, so that the parasitic inductance of the via hole will increase exponentially.
four. Via design in high speed PCB
Through the above analysis of the parasitic characteristics of the via, we can see that in the high-speed PCB design, seemingly simple vias will often have a great negative effect on the design of the circuit. In order to reduce the adverse effects of the via's parasitic effects, you can do as much as possible in your design:
1. Considering the cost and signal quality, choose a reasonably sized via size. For example, for a 6-10 layer memory module PCB design, 10/20 Mil (drill/pad) vias are preferred. For some high density, small size boards, 8/18 Mil can also be used. hole. Under current technical conditions, it is difficult to use smaller size vias. For power or ground vias, larger sizes can be considered to reduce the impedance.
2. The two equations discussed above can lead to the use of a thinner PCB board to help reduce the two parasitic parameters of the via.
3. The signal traces on the PCB are not changed as much as possible, which means that unnecessary vias should not be used.
4. The power and ground pins should be punched in the nearest hole. The shorter the lead between the via and the pin, the better, because they will cause the inductance to increase. At the same time, the leads of the power supply and ground should be as thick as possible to reduce the impedance.
5. Place some grounded vias near the signal layer vias to provide the signal with the closest loop. You can even place a lot of extra ground vias on the PCB board.
Of course, you need to be flexible when designing. The previously discussed via model is a case where there are pads on each layer, and sometimes we can reduce or even remove pads on some layers. Especially in the case of very high via density, it may lead to the formation of a broken channel in the copper layer, solving this problem. In addition to moving the location of the via, we can also consider the via in the copper layer. The pad size is reduced.
Source: PCB Information Network